The present invention relates to porous polyurethane polishing pads useful for polishing semiconductor substrates and a method of using the polishing pad. In addition, it relates to a method for forming the porous polishing pads.
In recent years, the requirements for integrated circuit fabrication and the drive toward ever higher circuit densities have made it critical that the surfaces of integrated circuit substrates (e.g., silicon wafers) and magnetic substrates (e.g., nickel-plated disks for memory applications) be polished to increasingly higher degrees of smoothness. The present state of the art for achieving the smoothest surface involves polishing the substrate using a polishing solution and a polishing pad.
One polishing technique for achieving a highly polished surface involves using a porous polishing pad in combination with a polishing slurry or reactive liquid. The porous polishing pad must be firm enough to provide the necessary polishing action while also being porous enough to hold the aqueous slurry or reactive liquid.
The most widely used materials for porous polishing pads are taken from a class of materials known as poromerics. Poromerics are textile-like materials having a multitude of pores or cells. Typically, the pores are formed using urethane-based impregnation or a porous coating layer. One method of forming poromeric pad material involves a solvent/non-solvent coagulation process. An example of such a process is described in U.S. Pat. No. 3,284,274 to Hulslander et al.
FIG. 1 is a close-up schematic cross-sectional view of a typical state-of-the-art poromeric polishing pad 6. Pad 6 has a top layer 10 with an upper surface 15. The top layer 10 contains cells 20 having a diameter anywhere from a few microns to several hundred microns.
The walls 30 of cells 20 can be solid, but more typically the walls are made up of microporous sponge. In a conditioned poromeric polishing pad 6, a large portion of cells 20 are open to surface 15 and form pores 35 therein.
Because the top poromeric layer 10 tends to be mechanically fragile, it is typically fixed on a substrate 40 such as a plastic film (e.g., Mylar™ polyethylene terephthalate film), heavy paper or a woven or non-woven textile (e.g., felt), sometimes by means of an adhesive.
To manufacture the poromeric layer 10 for pad 6 of FIG. 1, it is customary to coat a solution of polymer onto a substrate and then immerse the coated substrate into a bath that causes coagulation of the polymer. Once the polymer has been fully coagulated, the remaining solvent is leached out and the product dried.
Because of the nature of the coagulation process, cells 20 tend to increase in diameter as they penetrate deeper into the material. Also, a thin skin-layer (not shown) forms on the upper surface 15 of layer 10. The diameters of pores 35 at or near surface 15 are relatively small compared to the underlying cell diameters and get larger as material is removed from surface 15 during buffing. Likewise, the pore count at or near the (original) surface 15 is greater than when the pad is buffed down to create a new upper surface.
It is generally believed that having a pore count between 100 and 325 pores per mm2 is important to the polishing process. Specifically, it is believed that such a pore count allows the pad to carry (via cells 20) a large amount of slurry to the wafer (workpiece). To this end, the conventional poromeric pad polishing practice is to avoid a polishing surface with porosity. Typically, the number of pores per unit area, referred to as the “pore count,” is used to describe the polishing layer's porosity at the polishing surface. For purposes of this specification pore count refers to the average number of pores detectable per mm2 at an optical magnification of 50× on the polishing surface. A specific example of computer software useful for counting and processing pore data is Image-Pro Plus software, Version 4.1.0.1. The pore count is proportional to the (average) pore diameter, i.e., the higher the pore count, the smaller the average pore diameter.
This practice of maintaining sufficient pore size also eliminates several other detrimental side effects. For example, small pores make the pad short-lived because dross and spent slurry tend to clog the pores or get stuck in the underlying cells. Further, small pores can make it difficult to keep slurry flowing in and out of the cells. The dross can also become impacted in the cell and ultimately ends the cell's ability to carry slurry. Further, associated with small pores is a relatively high percentage of the pad surface area being composed of cell walls. This results in a high wiping friction while also decreasing the presentation of fresh slurry to the workpiece. In addition, at the end of the polishing cycle, it is a customary operating practice to rinse the substrate with pure water while the workpiece is still in the polishing environment. Relatively small cell openings take longer to flush the slurry out of the cells and replace it with fresh water.
It is customary therefore as part of the poromeric pad fabrication process to buff down the top layer by a distance D1 ranging from 4 to 6 mils in order to form the desired polishing surface. This buffing is performed immediately after the pad is fabricated. The result is a polishing surface 50 (dashed line) having a much larger pore size and smaller pore density than unbuffed surface 15. For example, polishing surface 50 has an average pore size between 100 and 325 pores per mm2, while the original surface did not contain any porosity.
The second step of a two-step polishing process for patterned semiconductor wafers typically forms a planarized surface after a bulk-removal polishing step. There is an ever-increasing demand to lower pad-induced defects during second-step and other CMP process steps for patterned wafers. In addition, there is an ongoing requirement for a process of producing polishing pads that further reduces defects in comparison to conventional porous polyurethane pads.